At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?

Process variability is introducing uncertainty in all the system level parametric specifications. Existing variability aware techniques can only capture and model the variations on system timing and leakage power. This paper proposes a framework that can capture variability in the dynamic energy consumption as well. It percolates variability information from semiconductor process to the Register Transfer Level. This enables to capture the application dynamics and provide an accurate estimation of dynamic energy along with leakage and timing.