DocumentCode :
2416351
Title :
Let´s study whole-program cache behaviour analytically
Author :
Vera, Xavier ; Xue, Jingling
Author_Institution :
Institutionen for Datateknik Malardalens Hogskola, Vasteras, Sweden
fYear :
2002
fDate :
2-6 Feb. 2002
Firstpage :
175
Lastpage :
186
Abstract :
Based on a new characterisation of data reuse across multiple loop nests, we preset a method, a prototyping implementation and some experimental results for analysing the cache behaviour of whole programs with regular computations. Validation against cache simulation using real codes shows the efficiency and accuracy of our method. The largest program, we have analysed, Applu from SPECfP95, has 3868 lines, 16 subroutines and 2565 references. In the case of a 32KB cache with a 32B line size, our method obtains the miss ratio with an absolute error of about 0.80% in about 128 seconds while the simulator used runs for nearly 5 hours on a 933MHz Pentium. III PC. Our method can be used to guide compiler locality optimisations and improve cache simulation performance.
Keywords :
cache storage; optimising compilers; program control structures; SPECfP95; cache behaviour; cache simulation performance; compiler locality optimisations; data reuse; multiple loop nests; prototyping implementation; regular computations; Boolean functions; Computer architecture; Data structures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Performance Computer Architecture, 2002. Proceedings. Eighth International Symposium on
ISSN :
1530-0897
Print_ISBN :
0-7695-1525-8
Type :
conf
DOI :
10.1109/HPCA.2002.995708
Filename :
995708
Link To Document :
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