Title :
Power issues related to branch prediction
Author :
Parikh, Dharmesh ; Skadron, Kevin ; Zhang, Yan ; Barcella, Marco ; Stan, Mircea R.
Author_Institution :
Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
Abstract :
This paper explores the role of branch predictor organization in power/energy/performance tradeoffs for processor design. We find that as a general rule, to reduce overall energy consumption in the processor it is worthwhile to spend more power in the branch predictor if this results in more accurate predictions that improve running time. Two techniques, however, provide substantial reductions in power dissipation without harming accuracy. Banking reduces the portion of the branch predictor that is active at any one time. And a new on-chip structure, the prediction probe detector (PPD), can use pre-decode bits to entirely eliminate unnecessary predictor and branch target buffer (BTB) accesses. Despite the extra power that must be spent accessing the PPD, it reduces local predictor power and energy dissipation by about 45% and overall processor power and energy dissipation by 5-6%.
Keywords :
microprocessor chips; parallel architectures; banking; branch predictor organization; branch target buffer accesses; on-chip structure; overall energy consumption; power dissipation; prediction probe detector; processor design; Accuracy; Banking; Computer science; Detectors; Embedded computing; Energy consumption; Energy dissipation; Power dissipation; Probes; Process design;
Conference_Titel :
High-Performance Computer Architecture, 2002. Proceedings. Eighth International Symposium on
Print_ISBN :
0-7695-1525-8
DOI :
10.1109/HPCA.2002.995713