DocumentCode
241647
Title
A novel scaling theory for fully depleted pi-gate (ПG) MOSFETs
Author
Chiang, Te-Kuang ; Gao, Hong-Wun ; Liu, Che-Wei ; Tsou, Tsung-Ying ; Chiu, Yi-Hung
Author_Institution
Dept. of Electrical Engineering of National University of Kaohsiung, Taiwan
fYear
2014
fDate
28-31 Oct. 2014
Firstpage
1
Lastpage
3
Abstract
A novel scaling theory for fully depleted pi-gate (ПG) MOSFETs is presented. The natural length for ПG MOSFET is obtained by solving the equation of equivalent number of gates (ENG), where the ENG of the ПG device monitored by the control factor η can be a linear combination of ENGs for both the triple-gate (TG) and quadruple-gate (QG) transistors. Numerical device simulation data for drain-induced barrier lowering (DIBL) were compared to the model to validate the theory. Among the ПG devices with the same normalized gate extension depth (NGED=tex /tsi ) in the buried oxide, one with the largest cross-section will show the worst immunity to DIBL effects due to the smallest ENG and largest natural length. For equivalent short-channel gate controlling capability, the ПG MOSFET with NGED =0.2 corresponding to the control factor of η=0.49 illustrates an improvement of up to 23% in the minimum effective channel length Lmin when compared to the double-gate (DG) MOSFET.
Keywords
Data models; Logic gates; MOSFET; Mathematical model; Numerical models; Threshold voltage; Voltage control; Equivalent number of gates (ENG); control factor; drain-induced barrier lowering (DIBL); natural length; normalized gate extension depth (NGED); pi-gate (ПG) MOSFETs;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location
Guilin, China
Print_ISBN
978-1-4799-3296-2
Type
conf
DOI
10.1109/ICSICT.2014.7021246
Filename
7021246
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