Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits

An efficient methodology for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits is presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This approach is shown to be accurate for both traditional CMOS logic and null convention logic (NCL) by correctly modeling critical gate characteristics. Simulations with different implementations of an 8051 processor core are in good agreement with measurements from a 0.25 mum CMOS test chip.