Title :
A global-aware bandwidth-constraint routing scheme for Network-on-Chip
Author :
Liulin Zhong ; Ming´e Jing ; Zhiyi Yu ; Xiaoyang Zeng
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
In this paper, we propose a global-aware, bandwidth-constraint, dead-lock free and low cost minimal routing algorithm for Network on Chip. The routing scheme generates routing paths based on the global condition of the network and it is supported by distributed minimal routing tables. Moreover, the proposed routing scheme can be easily adapted to high dimensional meshes and irregular topologies, making it promising for the 3D chips, fault-tolerant and heterogeneous chip multicore processors (CMP). The experimental results show that the proposed routing algorithm decreases the average latency of network by more than 25% compared with the popular routing schemes.
Keywords :
logic design; multiprocessing systems; network routing; network-on-chip; three-dimensional integrated circuits; 3D chips; distributed minimal routing tables; fault-tolerant heterogeneous chip multicore processors; global condition; global-aware bandwidth-constraint routing scheme; high dimensional meshes; low cost minimal routing algorithm; network-on-chip; routing paths; Abstracts; Bandwidth; IP networks; Network-on-chip; Routing; Solid modeling; System recovery;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021259
