A global-aware bandwidth-constraint routing scheme for Network-on-Chip

In this paper, we propose a global-aware, bandwidth-constraint, dead-lock free and low cost minimal routing algorithm for Network on Chip. The routing scheme generates routing paths based on the global condition of the network and it is supported by distributed minimal routing tables. Moreover, the proposed routing scheme can be easily adapted to high dimensional meshes and irregular topologies, making it promising for the 3D chips, fault-tolerant and heterogeneous chip multicore processors (CMP). The experimental results show that the proposed routing algorithm decreases the average latency of network by more than 25% compared with the popular routing schemes.