Future CMOS technology for low noise integrated circuit designs

Author

Chih-Hung Chen ; Wu, D.Y. ; Yi Ching Cheng ; Chao Sheng Chen

Author_Institution

Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

4

Abstract

This paper utilizes the recently defined equivalent noise sheet resistance to study the noise performance of future sub-100nm MOSFETs using strain engineering, channel engineering with III-V materials, and quantum-well structures for low-noise applications. Experimental results for devices fabricated in UMC´s five different CMOS technology nodes and other published data down to 20 nm technology node are demonstrated. Strategies for the future low-noise technologies are also discussed.

Keywords

CMOS integrated circuits; integrated circuit design; integrated circuit noise; integrated circuit technology; semiconductor quantum wells; CMOS technology nodes; III-V semiconductor materials; channel engineering; equivalent noise sheet resistance; future CMOS technology; future MOSFET; low noise applications; low noise integrated circuit designs; noise performance; quantum well structures; strain engineering; Abstracts; Computational modeling; Computers; Field effect transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021277

Filename

7021277