Influence of the interface charges´ location on the threshold voltage of pMOSFET

The effect of the interface charges´ location variation on the threshold voltage of pMOS device was numerically simulated. By dividing the interface into several regions, the relationship between that interface charges and the threshold voltage drift is well revealed combining the drain biasing conditions. In addition, we also investigated the mechanism of threshold voltage variation by comparing the surface potentials of various models. The study was helpful in pinpointing the critical device location where interface charges are more effective, which may promote the research on Drain Bias-Negative Bias Temperature Instability (DB-NBTI) effects.