A new low power unipolar CMOS

Although CMOS is the most popular technology for integrated circuits, a disadvantage is that it requires both NMOS and PMOS transistors. In contrast, this paper describes a new unipolar CMOS technology that replaces the PMOS transistor with a modified NMOS containing an elevated body and two embedded oxides (EBTEO). This modified NMOS makes use of the punch-through effect to achieve voltage-controlled on-off behavior. Two different gate work functions are performed for the unipolar CMOS to cause it to operate in the subthreshold region. Extended TCAD simulations are carried out to verify that the proposed EBTEO structure can obtain favorable inverter and logic gate output characteristics. Thus, it can be used for any CMOS logic circuits, including both static and dynamic logic families. By using different gate work functions for the unipolar CMOSs and allowing them to operate in the sub-threshold regime, the gate delay time can be reduced by more than 30 %, and the power consumption is also reduced greatly when compared with a conventional CMOS. Consequently, the EBTEO with SOI substrate significantly reduces the figure of merit, the delay-power product (DP), by more than 46 %.