• DocumentCode
    241736
  • Title

    An efficient test structure for interface trap characterization under BTI stresses

  • Author

    Yandong He ; Ganggang Zhang ; Lin Han ; Xing Zhang

  • Author_Institution
    Inst. of Microelectron., Peking Univ., Beijing, China
  • fYear
    2014
  • fDate
    28-31 Oct. 2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    An efficient test structure for interface trap density characterization has been proposed. Based on this single structure and one-time IV measurement, the interface trap densities on both n- and p-type Si/SiO2 interfaces are obtained, achieving 1x efficiency improvement and 50% cost reduction. BTI-stress-induced degradation was studied and compared under the same structure, demonstrating a better test efficiency and resolution to interface traps generation at different Si/SiO2 interfaces.
  • Keywords
    MOSFET; interface states; semiconductor device models; semiconductor device reliability; BTI stresses; IV measurement; Si-SiO2; interface trap density; n-type interfaces; p-type interfaces; Abstracts; Area measurement; Current measurement; Logic gates; Performance evaluation; Reliability; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4799-3296-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2014.7021291
  • Filename
    7021291
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=241736