A 12-bit 100-MSps pipelined-SAR ADC with a time-interleaved second-stage

In this paper, a 12-bit 100-MS/s pipelined-SAR ADC is presented. The design properly selects the resolution of the two pipeline stages and adopts time-interleaving technique to improve the speed. A split-capacitor DAC in 2^nd-satge SAR ADC and a “half gain” residue amplifier minimize the power dissipation. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 11.2b near the Nyquist input frequency at the sampling rate of 100MS/s. The power consumption is only 8.6mW with the supply voltage of 1.2V and the FoM is 36.6fJ/conv.-step operating at 100MS/s.