A parametrically drive PLL lock detector

A parametrically driven PLL lock detector is presented. The lock detector is described by a time-varying linear differential equation derived from the PPL´s nonlinear dynamics. The time-varying nature of this detector equation results from the fact that it is parametrically driven by the output of the PLL´s quadrature detector. A lock decision is made by comparing a detector equation state to a user-specified threshold. Also, the detector produces a DC voltage which may be capable of driving a phase locked receiver´s coherent AGC system. Finally, a laboratory experiment is described which demonstrate the feasibility of the detector concept. Use of the lock detector eliminates a class of problems associated with the simple phase quadrature lock detector, resulting from the fact that the quadrature detector can produce a DC component under false lock conditions