Challenges for InGaAs n-MOSFETs in the future generation sub-10nm CMOS logic devices

(1). The performance of n-MOSFETs in ultimate scaling limit (gate length approaches ballistic limit, gate oxide approaches quantum capacitance limit ) is assessed. Thick body (t_body>10nm) InGaAs channel with isotropic Γ conduction valley is not a good choice. The small conduction mass m_C* over-compensated by small density of states mass m_D*, leading to small drain current I_d. Ultrathin body t_body<;4nm InGaAs with [110] surface orientation can induce the lowest very anisotropic L valleys with large m_D*. When choosing the suitable channel direction with small m_C*, the FET may boost I_dsat to 15mA/μm at V_g-V_th=0.4V, increased by a factor of 6 comparing to the thick body with Γ valley conduction, and a factor of 30 comparing to the so far best record of I_dsat = 0.5mA/μm at 0.5V bias for the real InGaAs n-MOSFET. A FinFET structure on [100] InGaAs substrate with [110] Fin wall surface and <;4nm Fin width is proposed to implement the L valley conduction with largest I_dsat.