DocumentCode :
241832
Title :
Reducing memory requirements in CSA-based scalable Montgomery modular multipliers
Author :
Tao Wu
Author_Institution :
Shanghai Fudan Microelectron. Group Co. Ltd., Shanghai, China
fYear :
2014
fDate :
28-31 Oct. 2014
Firstpage :
1
Lastpage :
3
Abstract :
Scalable Montgomery modular multiplier is able to perform multiprecision Montgomery modular multiplications in limited hardware, but it requires memory units to store pipelined temporary results. These memory units are called FIFO, whose range increases as a result of longer operands. In this paper, two techniques are proposed to reduce the FIFO memory units in CSA-based scalable Montgomery modular multipliers by about 50%. They are then validated by synthesis results with an example.
Keywords :
digital arithmetic; logic design; multiplying circuits; semiconductor storage; CSA based scalable Montgomery modular multipliers; FIFO memory units; memory requirement reduction; CMOS integrated circuits; Hardware; Logic gates; Memory management; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
Type :
conf
DOI :
10.1109/ICSICT.2014.7021339
Filename :
7021339
Link To Document :
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