CORDIC-based VLSI architecture for implementing Log Polar Transformation for real time applications

In this work, a hardware efficient and flexible architecture has been proposed for computing Log Polar Transformation (LPT) for real time applications in image processing and pattern recognition. CORDIC (COordinate Rotational DIgital Computing) is used as a building block for our proposed architecture, so as to keep the design flexible that can be adapted to different specific applications. The basic philosophy of CORDIC algorithm is that it can be implemented using SHIFT and ADD/SUB units using VLSI technologies. Purely pipelined CORDIC architecture has been used to get high throughput. This proposed architecture has been simulated and synthesized using RTL Coding with Verilog-XL and Design Vision. The synthesized result shows that the circuit can be used with maximum frequency of 125 MHz with area 9.5 mm using 0.18 μm CMOS technology.