A systematic design methodology for yield-driven near-threshold SRAM design

8-T cell is proposed to improve stability and low-voltage operation in high-speed SRAM caches. However, the robustness consideration of near threshold SRAM design has not been included in the mainstream design methodology. In this work, taking 8-T cell as an example, it is the first time such a systematic design methodology guided by efficient yield analysis is applied to improve variability tolerance in high-speed SRAM operation. We draw support from the efficient form of importance sampling and boundary searching methods in order to get our design guide for a better yield. With our method, array-level 8-T SRAM design can work under near-threshold supply voltage with good performance and acceptable failure rate.