Title :
A 4.28 pJ/access high-density average-8T sub-threshold SRAM with reverse narrow-width effect (RNWE)-aware sizing
Author :
Khayatzadeh, Mahmood ; Yong Lian
Author_Institution :
EECS Dept., Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
This paper presents a sizing technique to strengthen the write and access transistors based on reverse narrow-width effect for sub-threshold SRAM in advanced CMOS technology. The technique is verified by a 16 kb SRAM chip in 65 nm technology. The measurement results show the chip consumes only 4.28 pJ/access in the best case with supply voltage as low as 0.27 V. Based on the average of measurements from 20 chips, the chip works from 30.8 kHz at 0.3 V while consuming 246 nW up to 2.42 MHz at 0.6 V while consuming 11.6 μW.
Keywords :
CMOS integrated circuits; SRAM chips; low-power electronics; RNWE-aware sizing; SRAM chip; advanced CMOS technology; frequency 2.42 MHz; frequency 30.8 kHz; power 11.6 muW; power 246 nW; reverse narrow-width effect; size 65 nm; storage capacity 16 Kbit; sub-threshold SRAM; voltage 0.27 V; voltage 0.3 V; voltage 0.6 V; write and access transistors; CMOS integrated circuits; CMOS technology; MOS devices; Random access memory; Semiconductor device measurement; Simulation; Transistors;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021365
