Title :
Design of D flip-flops with low power-delay product based on FinFET
Author :
Kai Liao ; Xiaoxin Cui ; Nan Liao ; Tian Wang
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
In this paper, FinFET has been introduced to the design of high performance D flip-flops. Based on the excellent electrical properties of FinFET, the SG-mode D flip-flop modified from original PHLFF by substituting SG-mode FinFET for planar MOSFET has a tremendous reduction of 87.0% on power-delay product (PDP). Considering the unique merits of multiple operating modes of FinFET, further optimization based on SG-mode PHLFF has been proposed to achieve lower PDP and more efficient area utilization rate. The simulation results indicate that the multi-mode PHLFF reduces the PDP by 92.6% and slightly decreases the number of transistors.
Keywords :
MOSFET circuits; flip-flops; logic design; low-power electronics; D-flip-flops; SG-mode PHLFF; low power delay product; multimode PHLFF; multiple operating mode FinFET; pulse generator-free hybrid latch based flip-flop; Abstracts; FinFETs;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021366
