A high parallel motion compensation implementation on a coarse-grained reconfigurable processor supporting H.264 high profile decoding

This paper presents a novel mapping method to implement the Motion Compensation algorithm/kernel of H.264/AVC decoder on a coarse-grained reconfigurable processor, called GReP (General-purpose Reconfigurable Processor). Reconfigurable processor have been proved to be the potential candidates for multimedia processing. However, there poor in processing control-intensive tasks and the ability to efficiently utilize the reconfigurable compute arrays become bottlenecks in many reconfigurable systems. This paper proposes a novel algorithm mapping method and several techniques to achieve those goals. With the proposed mapping method and techniques, the motion compensation task, which takes over half computation time in an H.264/AVC video decoder, consumes only 423~480 cycles per macroblock(MB) on GReP and also can support 1920×1080@30fps real-time decoding at 200MHz, with 10~50 times faster than some general purpose processors implementation.