Asynchronous reset design architecture

With the increased complexity of digital design, the reset architecture used in current nanometer-scale designs has become complicated. Design and implementation of reset architecture is therefore a crucial part of any design. This paper analyses the pros and cons of synchronous and asynchronous resets. We have presented our current understanding of reset design issues in real chip design when choosing reset strategy. Based on our rich industry experience, we are providing a practical, effective and reliable reset strategy, which will be applicable in modern nanometer-scale digital chip design.