• DocumentCode
    241959
  • Title

    A 1-G sample/S 71-dB SFDR CMOS S/H circuit

  • Author

    Chang Guo ; Rui Guan ; Dongpo Chen

  • Author_Institution
    Center for Analog/RF Integrated Circuits (CARFIC), Shanghai Jiao Tong Univ., Shanghai, China
  • fYear
    2014
  • fDate
    28-31 Oct. 2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    This paper presents a 1-Gsample/s sample and hold (S/H) circuit based on a source follower in a 40 nm SMIC CMOS process. Under the conception of modulating the bias current of source follower, a kind of technique is adopted to cancel its body effect and channel length modulation. This S/H achieves over 70dB spurious free dynamic range (SFDR) for a sine wave input with 402.3MHz and 1.6Vppd at 1GHz sampling frequency, 7dB more than the conventional structure. This S/H dissipates 17mW from a 2.5V supply.
  • Keywords
    CMOS integrated circuits; UHF integrated circuits; sample and hold circuits; SFDR CMOS S-H circuit; SMIC CMOS process; bias current modulation; body effect; channel length modulation; frequency 1 GHz; power 17 mW; sample and hold circuit; sampling frequency; sine wave input; size 40 nm; source follower; spurious free dynamic range; voltage 1.6 V; voltage 2.5 V; Abstracts; Degradation; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4799-3296-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2014.7021405
  • Filename
    7021405
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=241959