Title :
Pipeline of successive approximation converters with optimum power merit factor
Author :
Li, Jinghua ; Maloberti, Franco
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
A low power pipeline of successive approximation converter architecture is presented. It achieves 12-bit converter with 5 Msps. The converter consumes 4 mW when functioning at the Nyquist input frequency and using 1.8 V power supply. This entire circuit, simulated at the transistor level (0.18 μm CMOS process), achieves a FoM (Figure of Merit), as low as 0. 19 pJ/conversion.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; operational amplifiers; pipeline processing; timing; 0.18 micron; 1.8 V; 12 bit; 4 mW; CMOS ADC; Nyquist input frequency; low power pipeline; low-voltage AB class two stages amplifier; op-amp architecture; optimum power merit factor; successive approximation converter architecture; timing control; Bandwidth; CMOS technology; Capacitors; Clocks; Energy consumption; Magneto electrical resistivity imaging technique; Operational amplifiers; Pipelines; Sampling methods; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN :
0-7803-7596-3
DOI :
10.1109/ICECS.2002.1045322
