A radiation hardened scan flip-flop design with built-in soft error resilience

Author

Qiushi Wang ; Lin Jin

Author_Institution

No. 38 Res. Inst., IC Design Center, CETC, Hefei, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in scan flip-flop. The proposed radiation hardened scan flip-flop design (RH-SFF) takes use of time redundancy and space redundancy, which can tolerate soft error in sequential element and achieve about 20-fold reduction in SER of combinational logic, according to the circuit simulations using the an advanced 28nm technology. Comparing to the existing BISER flip-flop design, RH-SFF reduces the number of scan clock from 5 to 1, which enables the IC chips using the presented technique to be more testable in automatic test equipment (ATE), while achieves the same functions and delivers improved area, speed and power efficient.

Keywords

automatic test equipment; combinational circuits; flip-flops; logic design; radiation hardening (electronics); redundancy; sequential circuits; 20-fold reduction; ATE; BISER flip-flop design technique; IC chips; RH-SFF; SER; advanced technology; area improvement; automatic test equipment; built-in soft error resilience; circuit simulations; combinational logic; power efficient improvement; radiation hardened scan flip-flop design; radiation-induced soft errors; scan clock; sequential element; size 28 nm; space redundancy; speed improvedment; time redundancy; Clocks; Error correction; Flip-flops; Integrated circuits; Latches; Radiation hardening (electronics); Resilience;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021435

Filename

7021435