Title :
DSOI FET - A novel TID tolerant SOI transistor
Author :
Kai Zhao ; Xing Zhao ; Jiantou Gao ; Jinshun Bi ; Jiajun Luo ; Fang Yu ; Zhongli Liu
Author_Institution :
Inst. of Microelectron., Beijing, China
Abstract :
Charge trapping in the buried oxide can lead to serious back-channel leakage and make SOI (Silicon-on-Insulator) transistors more sensitive to total dose radiation. In this paper, a new DSOI (Double SOI) transistor is proposed, which utilizes the method of back-gate biasing to force an external electric field, and then depress the back channel formation during total dose irradiation. The simulation and testing results both indicate that, for a given structure, when a -3V bias is applied to the back-gate, the DSOI transistor can tolerant a total dose radiation of 500k rad(Si). This methodology fits all kinds of SOI MOSFETs, especially for the Fully-Depletion SOI transistors. With commercial (not especially hardened) buried oxide, DSOI device can have better radiation hardening performance than its both companions - FDSOI and PDSOI transistors.
Keywords :
MOSFET; radiation hardening (electronics); silicon-on-insulator; DSOI FET; FDSOI transistors; PDSOI transistors; SOI MOSFETs; TID tolerant SOI transistor; back-channel leakage; back-gate biasing method; buried oxide; charge trapping; double SOI transistor; external electric field; fully-depletion SOI transistors; radiation hardening performance; silicon-on-insulator; total dose irradiation; total dose radiation; voltage -3 V; Abstracts; CMOS integrated circuits; Field effect transistors; Logic gates; MOS devices; Substrates; System-on-chip;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021440
