The influence of temperature on dynamic gate-bias stress instability in amorphous silicon thin film transistors

Dynamic stress measurements were performed for a period of 12000 s on amorphous silicon (a-Si) thin-film transistors (TFTs) In order to investigate the influence of temperature on dynamic gate-bias stress instability, the tests were carried out at 40 °C, 70 °C and 100 °C respectively. The experimental results show that the performance of a-Si TFT is sensitive to the temperature. The electron de-trapping is dominant mechanism during the recovery phase at 40 °C, 70 °C. As temperature rises, the annealing of the defect states is enhanced. The influence of stress history on recovery is also discussed. On the whole, the temperature has great influence on instability of a-Si TFTs. Higher temperature cause worse subthreshold characteristics and accelerate the degradation of devices.