• DocumentCode
    2420556
  • Title

    Particle Swarm Optimization based vector reordering for low power testing

  • Author

    Kumar, S.Krishna ; Kaundinya, S. ; Kundu, Subhadip ; Chattopadhyay, Santanu

  • Author_Institution
    Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
  • fYear
    2010
  • fDate
    29-31 July 2010
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    In the sub 70 nm technologies, the leakage power dominates dynamic power. Most of the power calculation methods account for dynamic power dissipation and static leakage power dissipation, but the runtime leakage is generally neglected. It has been shown in recent studies that the contribution of runtime leakage power to the total power dissipation is not negligible any more. The dynamic power dissipation as well as the runtime leakage power depends on the sequence in which the test vectors are fed to it. This necessitates a pre-test phase to identify the sequence of test patterns to minimize the total power. Vector reordering problem is NP-complete and effective heuristic solutions have been proposed in the past. In this paper, we present an approach based on Particle Swarm Optimization (PSO), for vector reordering. PSO is based on the iterative use of a set of particles that correspond to states in an optimization problem, moving each agent in a numerical space looking for the optimal position. Experiments on ISCAS89 benchmark circuits validate the effectiveness of our work. Our approach obtained a maximum saving of 69.75% in the total number of transitions, 45.83% in peak transition, 68.05% in dynamic power, 42.56% in peak dynamic power, 0.38% in leakage power and 59.58% in total power dissipation over unordered test set.
  • Keywords
    electrical faults; electronic engineering computing; integrated circuit testing; low-power electronics; particle swarm optimisation; NP-complete; PSO; dynamic power dissipation; particle swarm optimization; power calculation methods; power testing; runtime leakage power; static leakage power dissipation; vector reordering problem; Capacitance; Integrated circuit modeling; Logic gates; Particle swarm optimization; Power dissipation; Runtime; Testing; CMOS; Dynamic power; leakage power; particle swarm optimization; vector reordering;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computing Communication and Networking Technologies (ICCCNT), 2010 International Conference on
  • Conference_Location
    Karur
  • Print_ISBN
    978-1-4244-6591-0
  • Type

    conf

  • DOI
    10.1109/ICCCNT.2010.5591871
  • Filename
    5591871