DocumentCode
2420757
Title
A reconfigurable wafer scale array for image processing
Author
Saucier, G. ; Patry, J.-L. ; Kouka, E.-F.
Author_Institution
Inst. Nat. Polytech. de Grenoble, France
fYear
1989
fDate
3-5 Jan 1989
Firstpage
277
Lastpage
288
Abstract
The defect tolerance strategy used in the design of a full wafer two-dimensional (2-D) array for image processing is discussed. Emphasis is placed on global architecture which is based partially on yield consideration. The soft switch network allows construction of the 2-D array even in the presence of defective processing elements (PEs). The configuration algorithm creates the target array with a very good harvest of functional PEs
Keywords
computer architecture; computerised picture processing; digital signal processing chips; configuration algorithm; defect tolerance strategy; defective processing elements; full-wafer 2-D array; global architecture; image processing; reconfigurable wafer scale array; soft switch network; yield consideration; Aluminum; Bandwidth; Image processing; Image storage; Rails; Registers; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9901-9
Type
conf
DOI
10.1109/WAFER.1989.47558
Filename
47558
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