A page buffer design based on stable and area-saving embedded SRAM for flash applications

Author

Huamin Cao ; Zongliang Huo ; Yu Wang ; Ting Li ; Jing Liu ; Lei Jin ; Dengjun Zhang ; Di Li ; Ming Liu

Author_Institution

Inst. of Microelectron., Beijing, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

This paper presents an embedded SRAM design for page buffer applications in flash memories. The page buffer was implemented with a newly proposed self-adaptive timing control circuit, an area-saving sense-latch circuit and 6T SRAM cell unit. A 2Kb SRAM macro with area of 135μm × 180μm has been implemented and applied in a 128Mb NOR flash memory with SMIC 65nm flash memory technology. Both simulation and chip test results show that SRAM page buffer is benefitial for high density flash memory design.

Keywords

NOR circuits; SRAM chips; buffer storage; flash memories; timing circuits; 6T SRAM cell unit; NOR flash memory; SMIC; SRAM macro; area-saving embedded SRAM; area-saving sense-latch circuit; flash memory technology application; page buffer design; self-adaptive timing control circuit; size 65 nm; static random-access memory; Abstracts; Latches; Optimization; Random access memory; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021465

Filename

7021465