An ultra-high speed DCFL dynamic frequency divider

Author

Ichioka, T. ; Tanaka, K. ; Saito, T. ; Nishi, S. ; Akiyama, M.

Author_Institution

Oki Electr. Ind. Co. Ltd., Tokyo, Japan

fYear

1989

fDate

12-13 June 1989

Firstpage

61

Lastpage

64

Abstract

The design, fabrication, and performance of a dynamic frequency divider is presented. The device operates with a single signal input, high speed, low power dissipation and a wide frequency range. It is implemented by 0.25- mu m-gate inverted high-electron-mobility transistors (I-HEMTs). The divider is operated in the frequency range of 1.8 GHz to 15 GHz with a power dissipation of 62 mW. The circuit has a maximum operating frequency of 26.5 GHz.<>

Keywords

MMIC; counting circuits; field effect integrated circuits; frequency dividers; integrated logic circuits; 1.8 to 26.5 GHz; 250 nm; 62 mW; DCFL; I-HEMTs; design; dynamic frequency divider; fabrication; frequency range; inverted HEMTs; inverted high-electron-mobility transistors; maximum operating frequency; performance; power dissipation; single signal input; Circuit synthesis; Coupling circuits; Frequency conversion; Latches; Logic circuits; Logic gates; Microwave circuits; Power dissipation; Propagation delay; Pulse inverters;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1989. Digest of Papers., IEEE 1989

Conference_Location

Long Beach, CA, USA

Type

conf

DOI

10.1109/MCS.1989.37263

Filename

37263