A parametric study of the effects of process parameters on the assembly of chip scale packages

Chip scale packaging (CSP) technology is developing in response to some of the limitations of flip chip technology. It addresses the concerns and perceived risk associated with handling and assembling bare die while maintaining most of the volumetric packaging and performance merits that flip chip technology offers. The assembly of chip scale packages is not a one step process, but requires optimisation of a variety of identified process parameters including solder volume. In this paper, we investigate the effects of some critical parameters on the assembly process and how they can be used to aid design. In addition, the self-alignment property is assessed