A method to design ternary multiplexers controlled by ternary signals based on SUS-LOC

In this paper, a method to design ternary multiplexers with any number of inputs is presented. The basic circuit used to design all ternary multiplexers is the 3-to-1 multiplexer. Starting from the basic multiplexer in binary, we design and simulate the 3-to-1 multiplexer. The multiplexer is built with the basic ternary functions such minimum and maximum. The control circuit of the 3-to-1 multiplexer is design with ternary circuits too, called indicators of logical level. Using one or more 3-to-1 ternary multiplexers, the ternary multiplexers with any number of inputs can be designed. All multiplexers are realized using Supplementary Symmetrical LOgic Circuit Structure (SUS-LOC). The operation of the multiplexers was proved by simulation in the Orcad environment.