Title :
Strained silicon nanowire tunnel FETs and NAND logic
Author :
Qing-Tai Zhao ; Knoll, Lars ; Richter, Simon ; Schulte-Braucks, Christian ; Gia Vinh Luong ; Blaser, Sebastian ; Schafer, Andreas ; Trellenkamp, Stefan ; Mantl, Siegfried
Author_Institution :
Peter Grunberg Inst. 9 (PGI 9-IT), Forschungszentrum Julich, Julich, Germany
Abstract :
We present strained Si TFETs with different architectures, from planar to highly down scaled gate all around (GAA) nanowire (NW) devices. Optimizing the TFET structure improves the electrostatics as required to enhance the tunneling currents. Furthermore, it suppresses trap assisted tunneling (TAT) and thus yields to steeper subthreshold slopes. We also demonstrate that a NAND Gate with GAA NW pTFET can be operated at VDD=0.2V. This demonstrates the great potential of TFETs for ultra low power application.
Keywords :
elemental semiconductors; field effect transistors; logic gates; nanowires; silicon; tunnelling; GAA NW devices; GAA NW pTFET; NAND gate; Si; TAT; TFET structure; electrostatics; gate all around nanowire devices; strained Si TFET; subthreshold slopes; trap assisted tunneling; tunneling currents; ultra low power application; voltage 0.2 V; Abstracts; Electric potential; Epitaxial growth; Hafnium compounds; Logic gates;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021495
