On-chip transimpedance preamplifier for CMOS BDJ optical detector using active enhanced impedance loads

A novel self-bias transimpedance preamplifier is proposed to be integrated on the same chip with a CMOS BDJ (buried double p-n junction) optical detector. This preamplifier is built with an input bias stage driving three transimpedance active loads. Its three output signals are respectively proportional to the detector´s photocurrents, I₁, I₂ and (I₁+I₂). These signals are needed for the detector to be operated either as a wavelength-sensitive detector and as a photodetector. The proposed circuitry is designed in a double-poly 0.8 μm CMOS technology, with no requirement for external component. It provides high transimpedance thanks to the use of regulated cascode transistors and implementation of bias-stabilization techniques. Transistor-level simulations show a DC transimpedance of 4 GΩ and a cutoff frequency of 18 Hz.