Top-down methodology based low-dropout regulator design using Verilog-A

This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.