A multitechnology test chip for university integrated circuit fabrication projects

Author

Fuller, L.F. ; Pearson, R.E. ; Price, D.T. ; Marz, H.C. ; Honan, T.L. ; Meisenzahl, E.J. ; Connor, J.

Author_Institution

Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA

fYear

1989

fDate

12-14 Jun 1989

Firstpage

56

Lastpage

59

Abstract

At Rochester Institute of Technology, a multitechnology test chip has been designed that has been in use for one year. The test chip has been incorporated in most of the fabrication runs, providing a large number of chips for probing. Each wafer processed has 40 test chips and 120 device chips. Each 4000×4000 μm test chip has seventeen 12 pad cells that contain a variety of test structures. In addition, there are eight cells for optical resolution and overlay structures for the various levels. The test chip has alignment marks for the GCA 4800 wafer stepper, Perkin Elmer scanners, and Kasper 2001 contact aligners. The authors describe the test chip, the structures on it, and the test system, and provide examples of the types of output that have been obtained

Keywords

education; integrated circuit technology; monolithic integrated circuits; student laboratory apparatus; 12 pad cells; GCA 4800 wafer stepper; Kasper 2001 contact aligners; Perkin Elmer scanners; Rochester Institute of Technology; alignment marks; device chips; multitechnology test chip; optical resolution; overlay structures; probing; university integrated circuit fabrication projects; Automatic testing; Circuit testing; Contact resistance; Data engineering; Fabrication; Integrated circuit testing; MOS devices; Microelectronics; System testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 1989. Proceedings., Eighth

Conference_Location

Westborough, MA

ISSN

0749-6877

Type

conf

DOI

10.1109/UGIM.1989.37300

Filename

37300