DocumentCode
2421649
Title
Measurement and simulation of interconnect capacitance variations
Author
Sauter, S. ; Rein, A. ; Frerichs, M. ; Schmitt-Landsiedel, D. ; Thewes, R. ; Weber, W.
Author_Institution
Corporate Res., Infineon Technol., Munich, Germany
fYear
2000
fDate
2000
Firstpage
64
Lastpage
67
Abstract
In the work we present results of capacitance measurements monitoring variations of the interconnect process. The measurements are compared with a 3D-simulation. The comparison shows that for a standard parasitics extraction the capacitance can be underestimated by up to 30% compared to measured results. In order to overcome this discrepancy, in our extraction, we consider fill structures, line widening for yield enhancement and process specific effects such as optical proximity and highly trapezoidal cross section of the conductors. This leads to good agreement between measured and extracted results. We also evaluate in detail the contribution of each effect to the total capacitance
Keywords
capacitance measurement; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; integrated circuit yield; proximity effect (lithography); 3D-simulation; capacitance measurements; fill structures; highly trapezoidal cross section; interconnect capacitance; interconnect process; line widening; optical proximity; process specific effects; standard parasitics extraction; yield enhancement; Capacitance measurement; Charge carrier processes; Circuit testing; Clocks; Fluid flow measurement; Integrated circuit interconnections; Manufacturing; Monitoring; Parasitic capacitance; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Statistical Metrology, 2000 5th International Workshop on
Conference_Location
Honolulu, HI
Print_ISBN
0-7803-5896-1
Type
conf
DOI
10.1109/IWSTM.2000.869313
Filename
869313
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