Title :
An efficient statistical model using electrical tests for GHz CMOS devices
Author :
Lee, Sang-Hoon ; Lee, Dong-Yun ; Kwon, Tae-Jin ; Lee, Joo-Hee ; Park, Young-Kwan ; Kim, Bum-Sik ; Kong, Jeong-Taek
Author_Institution :
CAE, Samsung Electron. Co. Ltd., Kyungki, South Korea
Abstract :
A practical statistical SPICE model has been developed for computer-aided design of high performance devices. This model accounts for both interdie and intra-die device variations, both of which contribute to statistical variations in chip performance. A new characterization method, ET-based SPICE modeling, is proposed in order to link the shift of E-tests (Electrical tests) to the SPICE input deck without additional measurements of I-V curves. Therefore, we can efficiently analyze the chip performance with respect to the process variations. The model is applied to a 2.0 V 1.6 GHz bandwidth DRAM which has 0.19 μm triple-well, 4-poly, 2-metal CMOS process. The simulated chip performance variability agrees well with measured data
Keywords :
CAD; CMOS integrated circuits; DRAM chips; SPICE; integrated circuit design; integrated circuit measurement; integrated circuit modelling; integrated circuit testing; statistical analysis; 0.19 mum; 1.6 GHz; 2.0 V; DRAM; ET-based SPICE modeling; GHz CMOS devices; SPICE input deck; chip performance; computer-aided design; efficient statistical model; electrical tests; high performance devices; inter-die device variations; intra-die device variations; process variations; simulated chip performance variability; statistical SPICE model; triple-well 4-poly 2-metal CMOS process; Bandwidth; CMOS process; Design automation; Electric variables measurement; Performance analysis; Random access memory; SPICE; Semiconductor device measurement; Semiconductor device modeling; Testing;
Conference_Titel :
Statistical Metrology, 2000 5th International Workshop on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-7803-5896-1
DOI :
10.1109/IWSTM.2000.869315
