Stacked-cascode Class-E power amplifier with delay-controlled auxiliary branches in 65nm CMOS

Low breakdown voltage in deep-submicron CMOS devices has limited the supply voltage and output power of power amplifiers (PAs). In this paper, a differential cascode Class-E PA in 65nm CMOS is proposed. Using only the standard devices, the stacked-cascode structure can endure a maximum voltage up to 10V so that a supply voltage of 3.3V is possible for Class-E PA. An auxiliary branch is added to reduce the turn-on resistance. With an inductor to delay the control signal phase of the branch, the proposed PA has a power dissipation trade-off between the devices´ on/off state. At 1.6GHz, the proposed Class-E PA achieves Power Added Efficiency (PAE) of 57.5% when it transmits 31.3dBm power.