DocumentCode :
242190
Title :
A gate leakage model for double gate tunneling field-effect transistors
Author :
Ying Zhu ; Lining Zhang ; Aixi Zhang ; Mansun Chan
Author_Institution :
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
fYear :
2014
fDate :
28-31 Oct. 2014
Firstpage :
1
Lastpage :
3
Abstract :
Thinner gate dielectric favors larger drivability of TFETs but also leads to larger gate leakage. In this work, an analytical model is presented to capture the gate leakage current in double gate tunneling FET with ultrathin oxide thicknesses. Its accuracy is verified by TCAD simulations. This gate leakage module has been integrated with our previous TFET model e-TuT and its implications on TFET-based inverters are presented.
Keywords :
dielectric materials; field effect transistors; leakage currents; logic gates; semiconductor device models; transistor circuits; tunnel transistors; TCAD simulations; TFET model; TFET-based inverters; double gate tunneling FET; double gate tunneling field-effect transistors; gate dielectric; gate leakage current; gate leakage model; gate leakage module; ultrathin oxide thicknesses; Abstracts; Analytical models; Equations; Logic gates; Mathematical model; Semiconductor device modeling; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
Type :
conf
DOI :
10.1109/ICSICT.2014.7021522
Filename :
7021522
Link To Document :
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