Title :
A low power high accuracy CMOS time-to-digital converter
Author :
Chen, Poki ; Liu, Shen-Iuan ; Wu, Jingshown
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, we present a new CMOS time-to-digital converter (TDC) with the cyclic delay line structure. The static supply current is 2-nA only. Furthermore, the continuous calibration is no longer needed. The TDC can be shunted down between measurements to make the power consumption negligible. The circuit with 64-stage cyclic delay line has been fitted into 0.25 mm×0.75 mm chip area with a typical 0.8-μm SPDM process. The measured resolution is 286 picoseconds, and the measured single-shot accuracy is less than 143 picoseconds. Both can be made much less if the control voltage is well tuned
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit tuning; delay lines; 0.8 micron; 143 ps; 2 nA; 286 ps; CMOS; SPDM process; continuous calibration; control voltage tuning; cyclic delay line structure; power consumption; single-shot accuracy; static supply current; time-to-digital converter; Calibration; Current supplies; Delay lines; Energy consumption; Linearity; Power measurement; Pulse circuits; Pulse measurements; Semiconductor device measurement; Voltage control;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.608704
