• DocumentCode
    242211
  • Title

    Adaptive Block level management for hybrid main memory

  • Author

    Renhua Yang ; Xiaoyong Xue ; Yufeng Xie ; Yinyin Lin

  • Author_Institution
    ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
  • fYear
    2014
  • fDate
    28-31 Oct. 2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    This paper proposes a PCM hybrid main memory management scheme called APABL (Adaptive PRAM aware Block-based LRU). Proposed scheme takes DRAM as the first memory and PCM as the spare memory. Only data evicted from DRAM is to be written into PCM. Our scheme can reduce both the access times to PCM and SSD without performance loss. Thus, it can also benefit the mobile computer.
  • Keywords
    DRAM chips; phase change memories; storage management chips; APABL; DRAM; PCM; adaptive PRAM; adaptive block level management; block-based LRU; hybrid main memory management scheme; Abstracts; Memory management; Phase change materials; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4799-3296-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2014.7021532
  • Filename
    7021532
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=242211