Title :
A new trench-planner gate MOSFET structure
Author :
Wang, Cailin ; Sun, Cheng ; Han, Junya
Author_Institution :
Xi´´an Univ. of Technol., Xi´´an, China
Abstract :
A new trench-planar gate MOSFET (TPMOS) structure is proposed, in which the shallow trench filled with n-type polysilicon is located at the center of n-drift region between two p-type regions. Compared with conventional VDMOS, the new structure´s on-resistance can reduce about 25%, the breakdown voltage can increase 10% and switching loss can retain immovability. Furthermore, the shallow trench structure can be realized by the existing etching process, and retains the advantage of simple technology and low cost. So it can further meet the need of higher voltage power switches application.
Keywords :
MOSFET; etching; power semiconductor switches; semiconductor device breakdown; silicon; TPMOS structure; VDMOS; breakdown voltage; etching process; higher voltage power switches; n-drift region; n-type polysilicon; shallow trench structure; switching loss; trench-planner gate MOSFET structure; Costs; Electric breakdown; Etching; Fabrication; Frequency; MOSFET circuits; Power MOSFET; Structural engineering; Switching loss; Voltage; etching; planar-trench gate; power MOSFET; power semicondctor devices;
Conference_Titel :
Power Electronics and Motion Control Conference, 2009. IPEMC '09. IEEE 6th International
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-3556-2
Electronic_ISBN :
978-1-4244-3557-9
DOI :
10.1109/IPEMC.2009.5157566
