Software and hardware development for C-V analysis of MOS capacitors for a laboratory course in process evaluation

Author

Jackson, M.A.

Author_Institution

Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY

fYear

1989

fDate

12-14 Jun 1989

Firstpage

83

Lastpage

86

Abstract

Hardware and software for data extraction from MOS capacitors via C-V analysis are described. Guidelines for minimizing and/or correcting noise, series resistance, leakage current, and parasitic capacitances in experimental apparatus are presented. A Fortran program for generating model 1 MHz and quasi-static C- V plots was written. By contrasting experimental curves to theory, the program extracts flatband voltage shift, oxide thickness, substrate doping, and interface traps. Examples of applications in theoretical discussions and IC process characterization are given

Keywords

capacitance measurement; computerised instrumentation; educational courses; metal-insulator-semiconductor devices; semiconductor device testing; student laboratory apparatus; C-V analysis; Fortran program; IC process characterization; MOS capacitors; data extraction; flatband voltage shift; hardware development; interface traps; laboratory course; leakage current; noise; oxide thickness; parasitic capacitances; process evaluation; series resistance; software development; substrate doping; Application specific integrated circuits; Data mining; Doping; Guidelines; Hardware; Leakage current; MOS capacitors; Parasitic capacitance; Semiconductor process modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 1989. Proceedings., Eighth

Conference_Location

Westborough, MA

ISSN

0749-6877

Type

conf

DOI

10.1109/UGIM.1989.37307

Filename

37307