Title :
Segmented unbalanced super junction LDMOS for power integrated circuits
Author :
Wenlian Wang ; Zhenhua Jia ; Yu Wang
Author_Institution :
Sch. of Instrum. & Electron., North Univ. of China, Taiyuan, China
Abstract :
A high voltage SOI LDMOS with segmented unbalanced super junction (SJ) is proposed for the power integrated circuits. The concentration of p-pillar is higher than that of n-pillar at source SJ, but the concentration of n-pillar is higher at drain SJ. Segmented unbalanced SJ structure improves the lateral electric field distribution while it relieves the substrate-assisted depletion effects, which increases the breakdown voltage (BV) of lateral SJ device. Three-dimensional device simulation results indicate that a BV of 300 V is achieved for the proposed device with drift length of 15μm, compared with 130 V for conventional one and 245 V for the buffered SJ structure.
Keywords :
MOS integrated circuits; electric fields; elemental semiconductors; power integrated circuits; silicon-on-insulator; SOI LDMOS; Si; breakdown voltage; electric field distribution; power integrated circuits; segmented unbalanced superjunction LDMOS; size 15 mum; substrate-assisted depletion effects; voltage 300 V; Abstracts; Substrates;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021543
