A 12b 200KS/s SAR ADC with novel capacitor switching procedure and digital background calibration

Modern biomedical application such as implanted systems calls for low power high performance analog-to-digital converters. The successive approximation register (SAR) architecture has been proved to be a best choice for its low power consumption and small die area, which benefits from CMOS technology. This work concentrates on a new capacitor array with a novel switching procedure to further improve power efficiency and area economy. The proposed SAR ADC is designed with a supply voltage of 1.8V and at a sampling rate of 200kS/s, and an SNDR of 67dB and power consumption of 6.2μW is achieved. The chip is implemented in 0.18μm SMIC CMOS technology and calibrated with LMS adaptive algorithm, leading to a 2~5dB increase in SNDR.