DocumentCode
2422381
Title
Asymmetric Core Computing
Author
Clarke, Jerry ; Shires, Dale ; Vines, John ; Mark, Eric
Author_Institution
Aberdeen Proving Ground, US Army Res. Lab. (ARL), Aberdeen, MD
fYear
2008
fDate
14-17 July 2008
Firstpage
361
Lastpage
365
Abstract
The free ride of increasing computing performance by constantly increasing processor frequency is coming to an end. The laws of physics combined with economic forces from the consumer electronics industry have created a revolution in computing which is now clearly headed toward "more" instead of "faster" processors. At the US Army Research Laboratory we have established a significant effort which is tasked with finding ways to take advantage of multi-core CPUs, Graphical Processing Units (GPUs), Cell Processors, and Field Programmable Gate Arrays (FPGAs) for both traditional physics-based simulations and real-time battlefield applications. Each of these technologies has various strengths and drawbacks. Our goal is to combine the asymmetric capabilities of the various cores into a complete high performance system. In this paper, we discuss the asymmetric core computing (ACC) Laboratory which we have established along with some of the software tools and applications we are developing.
Keywords
computer graphic equipment; field programmable gate arrays; parallel processing; asymmetric core computing; cell processors; consumer electronics industry; economic forces; field programmable gate arrays; graphical processing units; processor frequency; Application software; Computer industry; Consumer electronics; Electronics industry; Field programmable gate arrays; Frequency; Industrial economics; Laboratories; Military computing; Physics;
fLanguage
English
Publisher
ieee
Conference_Titel
DoD HPCMP Users Group Conference, 2008. DOD HPCMP UGC
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-3323-0
Type
conf
DOI
10.1109/DoD.HPCMP.UGC.2008.88
Filename
4755891
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