DocumentCode :
242239
Title :
A new DDFS based on unequal length piecewise linear approximation with one bit error correction
Author :
RuiTao Zhang ; Gang Chen ; Junan Zhang ; Guangbing Chen ; Jinshan Yu
Author_Institution :
Nat. Key Lab. of Sci. & Technol., Chongqing, China
fYear :
2014
fDate :
28-31 Oct. 2014
Firstpage :
1
Lastpage :
3
Abstract :
A new method has proposed for implementing phase to sinusoid amplitude conversion for 32 bits direct digital frequency synthesis (DDFS). It based on non-uniform piecewise linear approximation with one bit error correction. The main idea is partition the angle in the interval (0, π/2 ) into 64 non-uniform segments. Using linear function substitute approximates the sine function in every segment. The segments´ slope value and start point value need store (total 1408 Bits). Other sine value can calculate by an 11×7 multiplier and an 11 bits adder. Added one bit error implementing by combination logic into the 11 bits adder improve the SFDR of the DDFS. The RTL level simulation results show that the SFDR is 91.2dBc after correction without phase truncated when the output sine amplitude is 11 bit.
Keywords :
approximation theory; direct digital synthesis; error statistics; piecewise linear techniques; DDFS; RTL level simulation; bit error correction; direct digital frequency synthesis; nonuniform piecewise linear approximation; sine function; sinusoid amplitude conversion; storage capacity 11 bit; storage capacity 32 bit; unequal length piecewise linear approximation; Abstracts; Integrated circuits; Read only memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
Type :
conf
DOI :
10.1109/ICSICT.2014.7021546
Filename :
7021546
Link To Document :
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