DocumentCode :
2422486
Title :
Using Mitrion-C to Implement Floating-Point Arithmetic on a Cray XD1
Author :
Liu, Kevin K. ; Cameron, Charles B. ; Sarkady, Antal A.
Author_Institution :
Dept. of Electr. & Comput. Eng., US Naval Acad. (USNA), Annapolis, MD
fYear :
2008
fDate :
14-17 July 2008
Firstpage :
391
Lastpage :
395
Abstract :
Field-Programmable Gate Arrays (FPGAs) are of interest to the high performance computing (HPC) computing community because they offer lower power consumption and higher throughput compared to traditional processors. Recently, the implementation of floating-point operations on FPGAs has become possible as the amount of memory available on FGPAs has increased. Unfortunately, advances in technology have also increased the complexity of creating hardware designs for FPGAs. In this project, we describe our experiences using the Mitrion-C high-level language to implement floating-point calculations on a Cray XD1. We report resource consumption, throughput, and power consumption and conclude that Mitrion simplifies the hardware design process while successfully harnessing the computational power of FPGAs at little additional cost to power consumption.
Keywords :
high level languages; mainframes; Cray XD1; FPGA; Mitrion-C high level language; field programmable gate arrays; floating-point arithmetic; floating-point calculations; floating-point operations; hardware design process; high performance computing; Circuit simulation; Energy consumption; Field programmable gate arrays; Floating-point arithmetic; Hardware design languages; High level languages; High performance computing; Integrated circuit synthesis; Power engineering computing; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
DoD HPCMP Users Group Conference, 2008. DOD HPCMP UGC
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-3323-0
Type :
conf
DOI :
10.1109/DoD.HPCMP.UGC.2008.40
Filename :
4755898
Link To Document :
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