Polysilicon gate NMOS project for undergraduate laboratory

Several new processing capabilities have recently been commissioned in the RIT (Rochester Institute of Technology) microelectronic engineering laboratory. These include: (1) ion implantation; (2) LPCVD (low-pressure chemical vapor deposition) polysilicon; and (3) dry (plasma) etching. The development of these processes is part of a long-range goal to include CMOS technology in the undergraduate laboratory program. The object of this work was to develop a four-level NMOS process sequence utilizing these available processes in a way which would be suitable for an undergraduate laboratory project. The implementation of the project for a typical class is described, and some of the results and experiences are presented. A class of twenty students completed the project, including device design, wafer fabrication, and testing, in a period of six weeks, working six hours per week. Working devices were obtained, indicating that a base-line process is now available which can be optimized with further process development. The threshold voltage increased with increased implant dose, as expected