DocumentCode
2422595
Title
Improving Parallel Code Performance for Systems with Dual Processors
Author
Emeny, Susan ; Spetka, Scott ; Ramseyer, George ; Linderman, Richard
Author_Institution
ITT Corp., Rome, NY
fYear
2008
fDate
14-17 July 2008
Firstpage
418
Lastpage
423
Abstract
Modern multi-processor systems provide opportunities to improve parallel code implementation, thereby improving performance. Applying techniques for code improvement is still somewhat of an art, but a methodology to structure code changes is essential to success. We use a set of techniques to improve the performance of several existing codes for dual-processor systems. We take advantage of shared memories and shared local high speed networks as well as higher bandwidth for increasing numbers of components on processors and on boards. The techniques we introduce for dual-processor systems also apply to other multiprocessor systems, to exploit the advantages of low latencies and increasing cache sizes. We present parallel code performance improvement techniques and a methodology for applying them to existing codes. We use several codes to compare our results with theoretical peak performance and to illustrate our techniques and methodology. The results show that key techniques for code improvement work well with our methodology. We illustrate these techniques with examples will help developers to improve the performance of their codes.
Keywords
multiprocessing systems; parallel processing; cache size; dual processor system; multiprocessor system; parallel code performance; shared local high speed network; shared memory; Art; Bandwidth; Clocks; Computational fluid dynamics; Delay; High-speed networks; Laboratories; Multiprocessing systems; Switches; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
DoD HPCMP Users Group Conference, 2008. DOD HPCMP UGC
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-3323-0
Type
conf
DOI
10.1109/DoD.HPCMP.UGC.2008.39
Filename
4755903
Link To Document